Display backplane and fabrication method thereof, display panel and fabrication method thereof

A fabrication method of a display backplane, characterized in that the fabrication method comprises:

• providing an array substrate, the array substrate comprising at least one pixel unit, each pixel unit comprising at least one thin film transistor, and the at least one thin film transistor comprising a driving thin film transistor;
• forming a planarization layer covering the array substrate, the planarization layer being formed with a plurality of via holes, each of the plurality of via holes corresponding to the driving thin film transistor in one pixel unit;
• forming a pad layer comprising a plurality of pads on the planarization layer, a surface of the pad away from the planarization layer being a first surface, each pixel unit being provided with one of the plurality of pads, and the pad being electrically coupled to the driving thin film transistor in the pixel unit through the via hole which penetrates through the planarization layer;
• and
• forming a passivation layer covering the pad layer and comprising a plurality of through holes, each pad corresponding to one through hole, such that the first surface of the pad is exposed through a corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole.

A fabrication method of a display panel, characterized in that the fabrication method of the display panel comprises:

• providing an array substrate, the array substrate comprising at least one pixel unit, each pixel unit comprising at least one thin film transistor, and the at least one thin film transistor comprising a driving thin film transistor;
• forming a planarization layer covering the array substrate and formed with a plurality of via holes, each of the plurality of via holes corresponding to the driving thin film transistor in one pixel unit;
• forming a pad layer comprising a plurality of pads on the planarization layer, a surface of the pad away from the planarization layer being a first surface, each pixel unit being provided with one of the plurality of pads, and the pad being electrically coupled to the driving thin film transistor in the pixel unit through the via hole which penetrates through the planarization layer;
• forming a passivation layer to obtain a display backplane, the passivation layer covering the pad layer and comprising a plurality of through holes, each pad corresponding to one through hole, such that the first surface of the pad is exposed through a corresponding through hole, and an area of a top opening of the through hole is smaller than an area of a bottom opening of the through hole;
• and
• transferring a light emitting diode (LED) layer onto the display backplane such that each LED pin of the LED layer falls into a corresponding through hole and contacts with a corresponding pad;
• and
• soldering each LED of the LED layer with a corresponding pad through a corresponding LED pin.