Semiconductor protection device

A semiconductor protection device comprising:

• an N-type epitaxial layer;
• a device isolation layer on an upper surface of the N-type epitaxial layer;
• an N-type drift region below the device isolation layer;
• an N-type well in the N-type drift region;
• first and second P-type drift regions, each of the first and second P-type drift regions in contact with a respective opposite end of the device isolation layer, and spaced apart from the N-type drift region;
• first and second P-type doped regions, each of the first and second P-type doped regions in a respective one of the first and second P-type drift regions;
• first and second N-type floating wells, each of the first and second N-type floating wells in the respective one of the first and second P-type drift regions and spaced apart from a respective one of the first and second P-type doped regions, and wherein each of the first and second N-type floating wells is in contact with the respective one of the opposite ends of the device isolation layer;
• a first contact layer on the N-type epitaxial layer and in contact with the first N-type floating well and the device isolation layer;
• and
• a second contact layer on the N-type epitaxial layer and in contact with the second N-type floating well and the device isolation layer.

A semiconductor protection device comprising:

• a first conductivity-type epitaxial layer comprising first and second regions, wherein the first region comprises:
• a device isolation layer on an upper surface of the first conductivity-type epitaxial layer, wherein the device isolation layer overlaps a central axis of the semiconductor protection device;
• a first conductivity-type drift region below the device isolation layer;
• a first conductivity-type well in the first conductivity-type drift region;
• a second conductivity-type drift region in contact with the device isolation layer and spaced apart from the first conductivity-type drift region;
• a high voltage second conductivity-type well below the second conductivity-type drift region;
• a second conductivity-type doped region in the second conductivity-type drift region;
• a first conductivity-type floating well spaced apart from the second conductivity-type doped region in the second conductivity-type drift region;
• a contact layer on the first conductivity-type epitaxial layer, wherein the contact layer overlaps the first conductivity-type floating well and is in contact with the device isolation layer;
• and
• an electrode on the second conductivity-type doped region and spaced apart from the contact layer, and
• wherein the second region and the first region are mirror-symmetrical.