High electron mobility transistor and method of manufacturing the same

A high electron mobility transistor comprising:

• a channel layer comprising a 2-dimensional electron gas (2DEC);
• a barrier layer on the channel layer and comprising first regions and a second region, the first regions on portions of the channel layer and configured to induce the 2DEC of a first day density in the portions of the channel layer, and the second region on other portions of the channel layer and configured to induce the 2DEC of a second density different from the first density in the other portions of the channel layer;
• source and drain electrodes on the barrier layer;
• a gate electrode on the barrier layer between the source and drain electrodes;
• and
• a depletion formation layer between the barrier layer and the gate electrode,
• the first regions including a first edge region and a second edge region opposite each other with the second region in between,
• the first edge region and the second edge region corresponding respectively to both a first end and a second end of a surface of the channel layer crossing the gate electrode in plan view, wherein
• the barrier layer includes recesses in the first edge region and the second edge region,
• a thickness of the barrier layer in the recesses is greater than 0 nm and less than a thickness of the barrier layer in the second region,
• a portion of the gate electrode vertically overlapping the recesses is closer to the surface of the channel layer than a part of the gate electrode over the second region of the barrier layer,
• the depletion formation layer is configured to form a depletion region in the 2DEC, and
• the depletion formation layer comprises a p-type Group III-V nitride semiconductor.

A method of manufacturing a high electron mobility transistor comprising:

• forming a barrier layer on a channel layer;
• forming first regions and a second region of the barrier layer, the first regions configured to induce a 2DEG of a first density in portions of the channel layer and the second region configured to induce a 2DEG of a second density different from the first density in other portions of the channel layer;
• forming source and drain electrodes on the barrier layer;
• and
• forming a gate electrode on the barrier layer between the source and drain electrodes,
• the first regions including a first edge region and a second edge region opposite each other with the second region in between, the first edge region and the second edge region corresponding respectively to both a first end and a second end of a surface of the channel layer crossing the gate electrode in plan view, wherein
• the forming the first regions and the second region on the barrier layer comprises forming recesses in the first edge region and the second edge region of the barrier layer such that a thickness of the barrier layer in the recesses is greater than 0 nm and less than a thickness of the barrier layer in the second region,
• the gate electrode is formed on the barrier layer so a portion of the gate electrode vertically overlapping the recesses is closer to the surface of the channel layer than a part of the gate electrode over the second region of the barrier layer,
• the second region is not recessed,
• the source electrode and the drain electrode each have a longest dimension that extends parallel to each other in a first direction,
• the gate electrode has a longest dimension that extends in the first direction parallel to the longest dimension of each of the source electrode and drain electrode, and
• the first edge region and the second edge region are separated from each other in the first direction by the second region.