US 12,002,875 B2 · Semiconductor devices and methods of manufacture

Abstract

Semiconductor devices and methods of forming semiconductor devices are described herein. A method includes forming a first fin and a second fin in a substrate. A low concentration source/drain region is epitaxially grown over the first fin and over the second fin. The material of the low concentration region has less than 50% by volume of germanium. A high concentration contact landing region is formed over the low concentration regions. The material of the high concentration contact landing region has at least 50% by volume germanium. The high concentration contact landing region has a thickness of at least 1 nm over a top surface of the low concentration source/drain region.

Claims20

Dependent claims

A semiconductor device comprises:

a substrate having a first fin and a second fin;
an isolation region over the substrate between the first fin and the second fin;
a first semiconductor region over the first fin;
a second semiconductor region over the second fin, wherein the first semiconductor region and the second semiconductor region comprise a first concentration of germanium;
a third semiconductor region over the first semiconductor region and the second semiconductor region, the third semiconductor region comprises a second concentration of germanium greater than the first concentration, wherein the third semiconductor region separates the first semiconductor region and the second semiconductor region;
and
a source/drain contact, wherein at least a portion of the source/drain contact is in contact with the third semiconductor region.

4 more elements

A semiconductor device comprises:

a substrate having a first fin and a second fin;
an isolation region over the substrate between the first fin and the second fin;
a first merged source/drain region over the first fin and the second fin, the first merged source/drain region comprising:
a first epitaxial region over the first fin, the first epitaxial region comprising silicon germanium with a first concentration of germanium;
a second epitaxial region over the second fin, the second epitaxial region comprising silicon germanium with the first concentration of germanium, the first fin being spaced apart from the second fin;
and
a contact landing epitaxial region extending continuously over the first epitaxial region and the second epitaxial region, wherein the contact landing epitaxial region has a second concentration of germanium, wherein the second concentration of germanium is greater than the first concentration of germanium;
and
a source/drain contact extending into the contact landing epitaxial region, wherein a portion of the contact landing epitaxial region separates the source/drain contact from the first epitaxial region and the second epitaxial region.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/068,257Filed 19 Dec 2022 · continuation

Priority

28 May 2020

Published

US 2023/0123670 A120 Apr 2023

Granted

4 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/501
Field-effect transistors [FET]: fETs having stacked nanowire, nanosheet or nanoribbon channels

Family

Application63/031,095Us provisional application · filed 28 May 2020

Application17/167,731Parent of this continuation · filed 4 Feb 2021

US 2023/0123670 A1Pre-grant publication · published 20 Apr 2023

US 11,532,731 B2Parent of this continuation

US 2021/0376129 A1Published application

US 12,002,875 B2This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor devices and methods of manufacture

Life of this patent

Semiconductor devices and methods of manufacture

Life of this patent

Abstract

Claims20