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US 12,002,874 B2Granted
Buried power rail contact
AssigneeInternational Business Machines Corporation
InventorsJunli Wang, Ruilong Xie, Brent Anderson, Chen Zhang, Heng Wu
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a power rail contact at least partially disposed between a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure. The power rail contact is in contact with a buried power rail disposed under the first and second vertical fin structures. The power rail contact is in contact with at least one of the first and second source/drain regions. A contact cap is disposed above the power rail contact.
Claims20
A semiconductor structure comprising:
- a power rail contact at least partially disposed between opposing sidewalls of a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure, wherein a top surface of the power rail contact is below a top surface of the first source/drain region and the second source/drain region, and a bottom surface of the power rail contact is below a bottom surface of the first source/drain region and the second source/drain region;
- a buried power rail disposed under the first and second vertical fin structures, and on the bottom surface of the power rail contact;
- and
- a contact cap disposed above the power rail contact;
- wherein the first vertical fin structure comprises a metal-based gate layer disposed above the first source/drain region and in contact with a top surface of the contact cap;
- and
- wherein the first vertical fin structure and the second vertical fin structure together form a single vertical field-effect transistor and comprise the metal-based gate layer.
4 more elements
A semiconductor device comprising:
- a first vertical fin structure comprising a first source/drain region;
- a second vertical fin structure comprising a second source/drain region;
- a buried power rail disposed under the first and second vertical fin structures and below the first and second source/drain regions;
- a power rail contact at least partially disposed between opposing sidewalls of the first and second source/drain regions and in contact with the buried power rail, the power rail contact being in contact with at least one of the first and second source/drain regions, wherein a top surface of the power rail contact is below a top surface of the first source/drain region and the second source/drain region, and a bottom surface of the power rail contact is below a bottom surface of the first and second source/drain regions;
- and
- a contact cap disposed above the power rail contact;
- wherein the first vertical fin structure comprises a metal-based gate layer disposed above the first source/drain region and in contact with a top surface of the contact cap;
- and
- wherein the first vertical fin structure and the second vertical fin structure together form a single vertical field-effect transistor and comprise the metal-based gate layer.
6 more elements
An integrated circuit, comprising:
- one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
- a power rail contact at least partially disposed between opposing sidewalls of a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure, wherein a top surface of the power rail contact is below a top surface of the first source/drain region and the second source/drain region, and a bottom surface of the power rail contact is below a bottom surface of the first source/drain region and the second source/drain region;
- a buried power rail disposed under the first and second vertical fin structures, and on the bottom surface of the power rail contact;
- and
- a contact cap disposed above the power rail contact;
- wherein the first vertical fin structure comprises a metal-based gate layer disposed above the first source/drain region and in contact with a top surface of the contact cap;
- and
- wherein the first vertical fin structure and the second vertical fin structure together form a single vertical field-effect transistor and comprise the metal-based gate layer.
5 more elements
Dependencies are inferred from the claim text.