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US 12,002,872 B2Granted
Structure and formation method of semiconductor device structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chi Wu, Chai-Wei Chang, Kuo-Hui Chang, Yi-Cheng Chao
Life of this patent
Estimating the term…
Abstract
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.
Claims20
A semiconductor device, comprising:
- a gate stack over a semiconductor substrate, the gate stack comprising a gate dielectric layer, a work function layer, and a conductive fill layer, the work function layer extending along sidewalls and a bottommost surface of the conductive fill layer, wherein a topmost surface of the conductive fill layer is above a topmost surface of the gate dielectric layer in a cross-sectional view;
- a dielectric cap element over the gate stack, the dielectric cap element being in physical contact with the topmost surface of the conductive fill layer, a portion of the conductive fill layer protruding above a bottommost surface of the dielectric cap element in the cross-sectional view;
- a spacer element extending along a sidewall of the dielectric cap element and a sidewall of the gate stack, the spacer element having an inner sidewall closest to the sidewall of the gate stack, wherein a first portion of the gate dielectric layer is interposed between the work function layer and the semiconductor substrate, wherein a second portion of the gate dielectric layer is interposed between the work function layer and the spacer element;
- and
- a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a bottom surface of the spacer element.
2 more elements
A semiconductor device, comprising:
- a gate stack over a semiconductor substrate, the gate stack comprising a gate dielectric layer, a work function layer, and a conductive fill layer, the work function layer extending along opposing sides and a bottom of the conductive fill layer, the gate dielectric layer extending along sidewalls and a bottom of the work function layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer and a topmost surface of the gate dielectric layer in a cross-sectional view;
- a cap element over the gate stack, a portion of the cap element extending below the topmost surface of the conductive fill layer, the portion of the cap element comprising a dielectric material;
- a spacer element having a first portion extending along a sidewall of the gate stack and a second portion extending along a sidewall of the cap element, the first portion of the spacer element having a first width, the second portion of the spacer element having a second width, the first width being greater than the second width;
- and
- a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a bottom surface of the work function layer.
2 more elements
A semiconductor device, comprising:
- a gate stack over a semiconductor substrate, the gate stack comprising a work function layer and a conductive fill layer, the work function layer extending along sidewalls and a bottommost surface of the conductive fill layer, a topmost surface of the conductive fill layer being above a topmost surface of the work function layer in a cross-sectional view;
- a cap element over the gate stack, a dielectric material of the cap element being in physical contact with the topmost surface of the work function layer, a width of the cap element increasing as the cap element extends away from the topmost surface of the conductive fill layer and toward a topmost surface of the cap element;
- a spacer element on a sidewall of the cap element and a sidewall of the gate stack, wherein the spacer element has an inner sidewall facing the gate stack and the cap element, the inner sidewall having a lower portion with a first slope and an upper portion with a second slope, the second slope being less than the first slope, wherein the upper portion of the inner sidewall extends from the lower portion of the inner sidewall to a topmost surface of the spacer element, wherein at least a portion of the lower portion is above the topmost surface of the conductive fill layer in the cross-sectional view;
- and
- a source/drain region extending into the semiconductor substrate, a top surface of the source/drain region being above a top surface of the semiconductor substrate.
2 more elements
Dependencies are inferred from the claim text.