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US 12,002,850 B2Granted
Nanosheet-based semiconductor structure with dielectric pillar
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Julien Frougier, Ruilong Xie, Chanro Park
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Abstract
A semiconductor structure includes a substrate, a first device disposed on the substrate and a second device disposed on the substrate. The first device includes a first plurality of nanosheets comprising a p-type material. The second device includes a second plurality of nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first device and the second device.
Claims20
A semiconductor structure comprising:
- a first device disposed on a substrate, the first device comprising a first plurality of nanosheets, wherein the first plurality of nanosheets comprises a p-type material;
- a second device disposed on the substrate, the second device comprising a second plurality of nanosheets, wherein the second plurality of nanosheets comprises an n-type material;
- a dielectric isolation pillar extending vertically from within a top surface of the substrate and disposed between the first device and the second device;
- a first shallow trench isolation region disposed at least partially within the substrate on a first lateral side of the first plurality of nanosheets;
- and
- a second shallow trench isolation region disposed at least partially within the substrate on a first lateral side of the second plurality of nanosheets;
- wherein a second lateral side of the first plurality of nanosheets extends from a first lateral side of the dielectric isolation pillar and a second lateral side of the second plurality of nanosheets extends from a second lateral side of the dielectric isolation pillar;
- wherein each of the first plurality of nanosheets are in a staggered arrangement relative to each of the second plurality of nanosheets;
- and
- wherein the first plurality of nanosheets and the second plurality of nanosheets are each of a uniform width.
7 more elements
A semiconductor structure comprising:
- a dielectric isolation pillar extending vertically from within a top surface of a substrate;
- a pFET device comprising a first plurality of channel nanosheets disposed on a first lateral side of the dielectric isolation pillar and in contacting relation therewith;
- an nFET device comprising a second plurality of channel nanosheets disposed on a second lateral side of the dielectric isolation pillar and in contacting relation therewith;
- a first shallow trench isolation region disposed at least partially within the substrate on a first lateral side of the pFET device;
- and
- a second shallow trench isolation region disposed at least partially within the substrate on a first lateral side of the nFET device;
- wherein a second lateral side of the pFET device extends from the first lateral side of the dielectric isolation pillar and a second lateral side of the nFET device extends from the second lateral side of the dielectric isolation pillar;
- wherein each of the first plurality of channel nanosheets are in a staggered arrangement relative to each of the second plurality of channel nanosheets;
- and
- wherein the first plurality of channel nanosheets and the second plurality of channel nanosheets are each of a uniform width.
7 more elements
A method, comprising:
- forming a first device on a semiconductor substrate, the first device comprising a first plurality of nanosheets, wherein the first plurality of nanosheets comprises a p-type material;
- forming a second device on the semiconductor substrate, the second device comprising a second plurality of nanosheets, wherein the second plurality of nanosheets comprises an n-type material;
- forming a dielectric isolation pillar extending vertically from within a top surface of the semiconductor substrate between the first device and the second device;
- forming a first shallow trench isolation region at least partially within the semiconductor substrate on a first lateral side of the first plurality of nanosheets;
- and
- forming a second shallow trench isolation region at least partially within the semiconductor substrate on a first lateral side of the second plurality of nanosheets;
- wherein a second lateral side of the first plurality of nanosheets extends from a first lateral side of the dielectric isolation pillar and a second lateral side of the second plurality of nanosheets extends from a second lateral side of the dielectric isolation pillar;
- wherein each of the first plurality of nanosheets are in a staggered arrangement relative to each of the second plurality of nanosheets;
- and
- wherein the first plurality of nanosheets and the second plurality of nanosheets are each of a uniform width.
7 more elements
Dependencies are inferred from the claim text.