Power semiconductor device and manufacturing method thereof

A method for manufacturing a power semiconductor device, comprising:

• providing an epitaxial layer, wherein the epitaxial layer is of a first conductivity type and comprises an active region and a termination region;
• forming a first doped region in the epitaxial layer of the active region, wherein the first doped region is of a second conductivity type;
• forming a second doped region in the first doped region, wherein the second doped region is of the first conductivity type;
• forming a contact metal layer on the epitaxial layer, wherein the contact metal layer is in electrical contact with the second doped region, wherein the contact metal layer is not in contact with the first doped region of the second conductivity type;
• forming a device electrode in the active region, wherein the device electrode is located in a device trench extending into the epitaxial layer and is electrically isolated from the epitaxial layer and the contact metal layer;
• forming a first termination electrode in the termination region, wherein the first termination electrode is located in a first termination trench extending into the epitaxial layer and is electrically isolated from the epitaxial layer;
• forming a second termination electrode at a bottom of the first termination trench, wherein the second termination electrode is electrically isolated from the first termination electrode and the epitaxial layer, wherein both the first termination electrode and the second termination electrode are capable of being selectively floating or in electrical contact with the contact metal layer,
• forming a third termination electrode located in a second termination trench in the termination region awayfrom the active region, wherein the third termination electrode is electrically isolated from the epitaxial layer;
• and
• forming a fourth termination electrode located ata bottom of the second termination trench and electrically isolated from the third termination electrode and the epitaxial layer, wherein both the third termination electrode and the fourth termination electrode are capable of being selective floating or in electrical contact with the contact metal layer;
• forming a first dielectric isolating layer between the first termination electrode and the second termination electrode;
• forming a second dielectric isolating layer between the third termination electrode and the fourth termination electrode;
• forming a first dielectric layer on a bottom and sidewalls of the device electrode to isolate the device electrode from the epitaxial layer, wherein sidewalls and a bottom of the first dielectric layer are in contact with the epitaxial layer;
• forming second dielectric layers on bottoms and sidewalls of the second termination electrode and the fourth termination electrode to isolate the second termination electrode and the fourth termination electrode from the epitaxial layer, wherein sidewalls and a bottom of the second dielectric layers are in contact with the epitaxial layer;
• forming a doped well region extending from a surface of the epitaxial layer into the epitaxial layer;
• forming an annular doped region in the doped well region, wherein the annular doped region is separated from a periphery of the termination region by a distance;
• forming an insulating layer covering a part of a surface of the annular doped region;
• and
• forming a metal pad being in electrical contact with another part of the surface of the annular doped region and covering a part of a top surface of the insulating layer, wherein the contact metal layer continuously covers the second doped region and the first termination electrode to the third termination electrode from the device electrode.