Array substrate and manufacturing method thereof
AssigneeTcl China Star Optoelectronics Technology Co., Ltd.
InventorXu Huang
Life of this patent
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Abstract
The present application provides an array substrate and a manufacturing method thereof. The array substrate includes a substrate; an active layer comprising a channel region; a gate insulating layer; a gate corresponding to the channel region of the active layer; and a source and a drain disposed at opposite ends of the active layer, wherein the gate has a groove structure, the groove structure has an opening facing the active layer, and a region of the groove structure corresponding to the active layer is the channel region.
Claims14
An array substrate, comprising:
- a substrate;
- an active layer comprising a channel region;
- a gate insulating layer;
- a gate corresponding to the channel region of the active layer;
- and
- a source and a drain disposed at opposite ends of the active layer,
- wherein the gate has a groove structure, the groove structure has an opening facing the active layer, and a region of the groove structure corresponding to the active layer is the channel region,
- wherein the array substrate further comprises a buffer layer, the gate comprises a first gate and a second gate, and the gate insulating layer comprises a first gate insulating layer and a second gate insulating layer;
- wherein the substrate, the buffer layer, the first gate, the first gate insulating layer, the active layer, the second gate insulating layer, and the second gate are stacked in sequence;
- and
- wherein the buffer layer is disposed corresponding to the channel region of the active layer, the first gate has a groove structure covering opposite side surfaces and an upper surface of the buffer layer, the first gate insulating layer has a groove structure covering opposite side surfaces and an upper surface of the first gate, the active layer has a groove structure covering opposite side surfaces and an upper surface of the first gate insulating layer, the second gate insulating layer has a groove structure covering opposite side surfaces and an upper surface of the active layer, and the second gate covers opposite side surfaces and an upper surface of the second gate insulating layer.
A method of manufacturing an array substrate, comprising the following steps:
- step S10:
- forming a first metal layer on a buffer layer, and patterning the first metal layer to form a first gate;
- step S20:
- forming a first gate insulating layer on the first gate;
- step S30:
- forming an active layer on the first gate insulating layer, wherein the active layer comprises a channel region, a source contact region, and a drain contact region, and a drain contact region, and the source contact region and the drain contact region are spaced apart from each other by the channel region;
- step S40:
- forming a second gate insulating layer on the active layer;
- step S50:
- forming a second metal layer on the second gate insulating layer, and patterning the second metal layer to form a second gate corresponding to the channel region, a source in contact with the source contact region, and a drain in contact with the drain contact region;
- step S60:
- sequentially forming a passivation layer and a planarization layer on the second gate, the source, and the drain;
- and
- step S70:
- forming an electrode layer on the planarization layer.
Dependencies are inferred from the claim text.