Method to enhance 3D horizontal nanosheets device performance
AssigneeTokyo Electron Limited
InventorsMark I. Gardner, H. Jim Fulford
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Abstract
Aspects of the present disclosure provide a method of fabricating a semiconductor device including a plurality of vertically stacked transistors. For example, the method can include providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors. The method can further include uncovering the second layers. The method can further include forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors.
Claims20
A method of fabricating a semiconductor device including a plurality of vertically stacked transistors, comprising:
- providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors;
- uncovering the second layers;
- forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors;
- and
- forming a second shell on a second one of the uncovered second layers, the second shell and the second one of the uncovered second layers forming a second channel structure of a second one of the transistors, wherein the first channel structure is a P-type channel structure, and the second channel structure is an N-type channel structure, or
- forming a second shell on a second one of the uncovered second layers, the second shell and the second one of the uncovered second layers forming a portion of a second channel structure of a second one of the transistors, wherein the first and second shells include different materials.
A method of fabricating a semiconductor device including a plurality of vertically stacked transistors, comprising:
- providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors;
- uncovering the second layers;
- and
- forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors,
- wherein providing a vertical stack of alternating horizontal first and second layers includes bonding two sub-stacks of alternating horizontal first and second layers.
A semiconductor device, comprising:
- a vertical stack of horizontal channels of a plurality of transistors;
- a first shell formed on a first one of the channels, the first shell and the first one of the channels forming a first channel structure of a first one of the transistors;
- and
- a second shell formed on a second one of the channels, the second shell and the second one of the channels forming a second channel structure of a second one of the transistors, wherein the first channel structure is a P-type channel structure, and the second channel structure is an N-type channel structure, or
- a second shell formed on a second one of the channels, the second shell and the second one of the channels forming a second channel structure of a second one of the transistors, wherein the first and second shells include different materials.
Dependencies are inferred from the claim text.