US 12,002,808 B2 · Dual dielectric pillar fork sheet device

Abstract

A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.

Claims20

Dependent claims

A forksheet nanosheet semiconductor device fabrication method comprising:

forming a plurality of channel nanosheet layers upon a substrate;
forming a dielectric pillar comprising a first dielectric within the, plurality of channel nanosheet layers thereby forming a first nanosheet stack directly against a first sidewall of the dielectric pillar and a second nanosheet stack directly against a second sidewall of the dielectric pillar;
forming a pair of sacrificial gate structures around the first nanosheet stack and around the second nanosheet stack;
forming a trench within the dielectric pillar self-aligned to and between the pair of sacrificial gate structures;
and
forming a second dielectric different than the first dielectric within the trench to form a dual dielectric pillar.

3 more elements

A forksheet semiconductor device comprising:

a first side separated from a second side by a dual dielectric pillar that comprises a first sidewall that faces the first side, a second sidewall that faces the second side, a first dielectric, and a second dielectric that is different from the first dielectric;
a first source/drain region within the first side that is directly connected to the second dielectric of the first sidewall of the dual dielectric pillar;
a second source/drain region within the second side that is directly connected to the second dielectric of the second sidewall of the dual dielectric pillar;
and
an in-line gate structure comprising a first gate within the first side and a second gate within the second side, wherein the first gate is directly connected to the first dielectric of the first sidewall of the dual dielectric pillar and the second gate is directly connected to the first dielectric of the second sidewall of the dual dielectric pillar.

2 more elements

Dependencies are inferred from the claim text.

Dual dielectric pillar fork sheet device

Life of this patent

Dual dielectric pillar fork sheet device

Life of this patent

Abstract

Claims20