Semiconductor package and method of fabricating the same

A semiconductor package, comprising:

• a first semiconductor chip mounted on a substrate;
• a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip;
• a second semiconductor chip disposed on the first semiconductor chip and the first conductive post;
• a third semiconductor chip mounted on the substrate and horizontally spaced apart from the first semiconductor chip, and
• a mold layer on the substrate that covers the first semiconductor chip, the second semiconductor chip, and the first conductive post,
• wherein the second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal, and the first dummy solder terminal is between the first semiconductor chip and the second semiconductor chip,
• the second semiconductor chip is coupled to the first conductive post by a first signal solder terminal, and the first signal solder terminal is between the first conductive post and the second semiconductor chip,
• the first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip,
• wherein the semiconductor package further comprises:
• a second conductive post disposed on the substrate and spaced apart from the first semiconductor chip;
• and
• a third semiconductor chip disposed on the first semiconductor chip and the second conductive post, and horizontally spaced apart from the second semiconductor chip,
• wherein the third semiconductor chip is supported by a second dummy solder terminal disposed between the first semiconductor chip and the third semiconductor chip,
• the third semiconductor chip is coupled to the second conductive post through a second signal solder terminal disposed between the second conductive post and the third semiconductor chip,
• the second dummy solder terminal is in direct contact with the top surface of the first semiconductor chip, and is electrically disconnected from the third semiconductor chip.

A semiconductor package, comprising:

• a first semiconductor chip mounted on a substrate;
• a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip;
• a second semiconductor chip disposed on the first semiconductor chip and the first conductive post;
• a third semiconductor chip mounted on the substrate and horizontally spaced apart from the first semiconductor chip, and
• a mold layer on the substrate that covers the first semiconductor chip, the second semiconductor chip, and the first conductive post,
• wherein the second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal, and the first dummy solder terminal is between the first semiconductor chip and the second semiconductor chip,
• the second semiconductor chip is coupled to the first conductive post by a first signal solder terminal, and the first signal solder terminal is between the first conductive post and the second semiconductor chip, and
• the first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip,
• wherein the second semiconductor chip overlaps a portion of the first semiconductor chip and a portion of the third semiconductor chip,
• the second semiconductor chip is disposed on the third semiconductor chip and is supported by a third dummy solder terminal disposed between the second semiconductor chip and the third semiconductor chip, and
• the first conductive post is disposed between the first semiconductor chip and the third semiconductor chip, and connects the second semiconductor chip to the substrate.