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US 12,002,784 B2Granted
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorYun Seok Choi
Life of this patent
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Abstract
A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.
Claims18
A semiconductor package comprising:
- an upper substrate having a first surface and a second surface opposite to each other,
- a lower semiconductor chip on the first surface of the upper substrate;
- a plurality of conductive pillars on the first surface of the upper substrate and at least one side of the lower semiconductor chip;
- a lower mold layer on the first surface of the upper substrate, the lower mold layer filling a space between the lower semiconductor chip and the plurality of conductive pillars;
- a plurality of upper semiconductor chips on the second surface of the upper substrate, the plurality of upper semiconductor chips include a first upper semiconductor chip and a second upper semiconductor chip laterally spaced apart from each other in a first direction parallel to the second surface of the upper substrate and electrically connected to the second surface of the upper substrate;
- upper bumps between the first upper semiconductor chip and the second surface of the upper substrate and the second upper semiconductor chip and the second surface of the upper substrate;
- and
- upper underfill layers respectively disposed between the first upper semiconductor chip and the second surface of the upper substrate and the second upper semiconductor chip and the second surface of the upper substrate,
- wherein the lower semiconductor chip vertically overlaps a portion of the first upper semiconductor chip and a portion of the second upper semiconductor chip in a second direction perpendicular to the second surface of the upper substrate,
- wherein the lower semiconductor chip includes lower through-electrodes penetrating therethrough, one of the lower through-electrodes vertically overlaps the portion of the first upper semiconductor chip in the second direction, and another of the lower through-electrodes vertically overlaps the portion of the second upper semiconductor chip in the second direction,
- wherein the upper underfill layers are laterally spaced apart from each other in the first direction, and each of the upper underfill layers covers corresponding ones of the upper bumps,
- wherein the lower semiconductor chip and the plurality of conductive pillars are electrically connected to the first surface of the upper substrate.
9 more elements
A semiconductor package comprising:
- an upper substrate having a first surface and a second surface opposite to each other;
- a lower semiconductor chip on the first surface of the upper substrate;
- a lower mold layer on the first surface of the upper substrate, the lower mold layer covering the lower semiconductor chip;
- and
- a plurality of upper semiconductor chips on the second surface of the upper substrate, the plurality of upper semiconductor chips include a first upper semiconductor chip and a second upper semiconductor chip laterally spaced apart from each other in a first direction parallel to the second surface of the upper substrate,
- wherein the lower semiconductor chip is electrically connected to the first surface of the upper substrate,
- wherein the first and second upper semiconductor chips are different kinds of semiconductor chips and are electrically connected to the second surface of the upper substrate,
- wherein the lower semiconductor chip vertically overlaps a portion of the first upper semiconductor chip and a portion of the second upper semiconductor chip in a second direction perpendicular to the second surface of the upper substrate, and
- wherein the lower semiconductor chip includes lower through-electrodes penetrating therethrough, one of the lower through-electrodes vertically overlaps the portion of the first upper semiconductor chip in the second direction, and another of the lower through-electrodes vertically overlaps the portion of the second upper semiconductor chip in the second direction.
6 more elements
Dependencies are inferred from the claim text.