Passivation scheme for pad openings and trenches

An integrated circuit comprising:

• a substrate;
• an interlayer dielectric (ILD) layer overlying the substrate, wherein the ILD layer at least partially defines a trench, and wherein the trench extends vertically through the ILD layer from a top of the ILD layer to the substrate and further extends laterally in a closed path along an edge of the integrated circuit;
• and
• a passivation layer overlying the ILD layer, wherein the passivation layer lines a sidewall of the ILD layer in the trench, and wherein the passivation layer has a curved portion.

An integrated circuit comprising:

• a substrate;
• a semiconductor device on the substrate;
• an interlayer dielectric (ILD) layer overlying the semiconductor device;
• a plurality of wires and a plurality of vias in the ILD layer, wherein the plurality of wires and the plurality of vias are alternatingly stacked over and define a conductive path leading from the semiconductor device;
• and
• a passivation layer overlying the ILD layer, wherein the passivation layer lines a sidewall of the ILD layer in a trench at a periphery of the integrated circuit and further has a lower water vapor transmission rate than the ILD layer;
• wherein the passivation layer at least partially defines a protrusion extending vertically to the substrate through the trench.