Integrated circuit package and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Shi Liu, Jiun Yi Wu, Chien-Hsun Lee
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Shi Liu, Jiun Yi Wu, Chien-Hsun Lee
Estimating the term…
In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 μm to 30 μm; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.
A device comprising:
A device comprising:
A device comprising:
Dependencies are inferred from the claim text.