Integrated circuit device and electronic system including the same

An integrated circuit device comprising:

• a base structure;
• a gate stack on the base structure, wherein the gate stack comprises a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to a main surface of the base structure;
• a plurality of channel structures that penetrate the gate stack and contact the base structure, wherein each of the plurality of channel structures comprises a respective alignment key that protrudes from the gate stack;
• a first upper insulating layer on the gate stack, wherein the first upper insulating layer comprises a key opening that overlaps the plurality of channel structures in the first direction;
• a second upper insulating layer in the key opening of the first upper insulating layer, wherein the second upper insulating layer overlaps the respective alignment key of each of the plurality of channel structures, and wherein the second upper insulating layer comprises a recessed portion at an upper side thereof;
• a buried insulating pattern in the recessed portion of the second upper insulating layer;
• a top supporting layer on the second upper insulating layer, wherein the top supporting layer is on the buried insulating pattern;
• a bit line on the top supporting layer;
• and
• a plurality of bit line contacts that penetrate the second upper insulating layer, the buried insulating pattern, and the top supporting layer, wherein respective ones of the plurality of bit line contacts electrically connect respective ones of the plurality of channel structures to the bit line.

An electronic system comprising:

• a main substrate;
• an integrated circuit device on the main substrate;
• and
• a controller on the main substrate, wherein the controller is electrically connected to the integrated circuit device,
• wherein the integrated circuit device comprises:
• a base structure;
• a peripheral circuit structure on the base structure;
• an input/output pad electrically connected to the peripheral circuit structure;
• a gate stack on the peripheral circuit structure, wherein the gate stack comprises a plurality of gate electrodes spaced apart from each other in a first direction perpendicular to a main surface of the base structure;
• a plurality of channel structures that extend in the first direction and penetrate the gate stack, each of the plurality of channel structures comprising a respective alignment key that protrudes from the gate stack;
• a first upper insulating layer on the gate stack, wherein the first upper insulating layer comprises a key opening that overlaps the plurality of channel structures in the first direction, wherein a sidewall of the key opening comprises a first step;
• a second upper insulating layer in the key opening of the first upper insulating layer, wherein the second upper insulating layer is on the respective alignment key of each of the plurality of channel structures;
• a top supporting layer on the second upper insulating layer;
• a bit line on the top supporting layer;
• and
• a plurality of bit line contacts that penetrate the second upper insulating layer and the top supporting layer and electrically connect respective ones of the plurality of channel structures to the bit line.