Semiconductor device, stacked semiconductor device and manufacturing method of semiconductor device

A stacked semiconductor device, comprising:

• a first semiconductor device comprising:
• a first semiconductor substrate;
• a first surface dielectric layer disposed over the first semiconductor substrate;
• a first circuit layer embedded in the first surface dielectric layer;
• a first electrical and thermal conductive layer in physical contact with the first circuit layer, wherein a thermal conductivity of the first electrical and thermal conductive layer is substantially greater than a thermal conductivity of the first circuit layer;
• and
• a first electrical insulating and thermal conductive layer covering a first outer surface of the first surface dielectric layer, wherein a thermal conductivity of the first electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the first surface dielectric layer;
• and
• a second semiconductor device disposed over and bonded to the first semiconductor device, comprising:
• a second semiconductor substrate;
• a second surface dielectric layer disposed over the second semiconductor substrate;
• and
• a second electrical insulating and thermal conductive layer covering a second outer surface of the second surface dielectric layer and in physical contact with the first electrical insulating and thermal conductive layer.

A manufacturing method of a semiconductor device, comprising:

• forming an electrical insulating and thermal conductive layer over a semiconductor substrate;
• forming a dielectric structure over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure;
• forming a stepped opening in the dielectric structure, wherein the opening extending through the dielectric structure and the electrical insulating and thermal conductive layer;
• forming a circuit layer in the dielectric structure by a damascene process, wherein the circuit layer fills the stepped opening and comprises a bottom surface closest to the semiconductor substrate, and a lower surface of the electrical insulating and thermal conductive layer is substantially coplanar with the bottom surface of the circuit layer.