Metallization layer and fabrication method

A method, comprising:

• providing a substrate having a first region and a second region;
• forming a first metallization layer over the substrate, wherein the first metallization layer comprises a wire;
• forming an array of devices in the first region, wherein the devices include a top electrode;
• depositing a dielectric layer in the second region, wherein the dielectric layer rises at least to a height of the top electrode;
• forming a hole that goes through the dielectric layer, wherein the wire is exposed through the hole;
• inducing metal from the wire to migrate into the hole so as to form a via in the hole, wherein inducing metal from the wire to migrate into the hole comprises alternately oxidizing and reducing the metal from the wire;
• and
• planarizing, wherein planarizing makes upper surfaces of the via and the top electrode coplanar.

A method comprising:

• providing a semiconductor substrate, wherein a wire comprising metal is disposed over the semiconductor substrate;
• depositing a dielectric layer over the wire;
• etching a hole through the dielectric layer, wherein the wire is exposed at a bottom of the hole;
• exposing the wire to a gas, wherein the gas causes some of the metal in the wire to migrate upward into the hole by alternately oxidizing and reducing the metal, and the metal that migrates upward into the hole forms a metal structure in the hole.