Barrier and air-gap scheme for high performance interconnects

A semiconductor structure, comprising:

• a semiconductor substrate;
• a dielectric layer disposed over the semiconductor substrate;
• a first via disposed within the dielectric layer extending from the semiconductor substrate to a bottom surface of a first metal cap, wherein the first metal cap extends from a top surface of the first via to a top surface of the dielectric layer;
• a glue layer structure disposed over the first metal cap;
• a metal line extending from the glue layer structure to a second via;
• a first pair of barrier layer structures disposed along sidewalls of the glue layer structure and metal line from above the dielectric layer to a top surface of the metal line;
• and
• a second pair of barrier layer structures separated from the first pair of barrier layer structures by a pair of cavities, wherein the pair of cavities are along a top surface of the dielectric layer and inner sidewalls of the second pair of barrier layer structures and outer sidewalls of the first pair of barrier layer structures.

A method of forming a semiconductor device, comprising:

• forming a dielectric layer over a semiconductor substrate;
• forming a metal layer above the dielectric layer;
• forming a hard mask layer over the metal layer;
• patterning the metal layer and hard mask layer to expose a top surface of the dielectric layer and define a pair of metal lines laterally separated from one another;
• forming a blocking structure along the top surface of the dielectric layer, and along a top surface and sidewalls of the hard mask layer while leaving inner sidewalls of the pair of metal lines exposed;
• while the blocking structure is present, selectively forming a barrier layer structure along the inner sidewalls of the pair of metal lines;
• and
• removing the blocking structure to form a cavity defined by the top surface of the dielectric layer and inner sidewalls of the barrier layer structure.