US 12,002,717 B2Granted

Semiconductor device and method

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorShahaji B. More

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Abstract

An embodiment device includes: first fins protruding from an isolation region; second fins protruding from the isolation region; a first fin spacer on a first sidewall of one of the first fins, the first fin spacer disposed on the isolation region, the first fin spacer having a first spacer height; a second fin spacer on a second sidewall of one of the second fins, the second fin spacer disposed on the isolation region, the second fin spacer having a second spacer height, the first spacer height greater than the second spacer height; a first epitaxial source/drain region on the first fin spacer and in the first fins, the first epitaxial source/drain region having a first width; and a second epitaxial source/drain region on the second fin spacer and in the second fins, the second epitaxial source/drain region having a second width, the first width greater than the second width.

Claims20

Dependent claims

A method comprising:

forming a first fin and a second fin protruding from an isolation region;
depositing a first dielectric layer on the first fin;
depositing a second dielectric layer on the second fin;
patterning the first dielectric layer to form first fin spacers adjacent the first fin and on the isolation region, the first fin spacers having a first spacer height;
patterning the second dielectric layer to form second fin spacers adjacent the second fin and on the isolation region, the second fin spacers having a second spacer height, the first spacer height being greater than the second spacer height;
growing a first epitaxial source/drain region in the first fin and on the first fin spacers, the first epitaxial source/drain region having a first width, the first epitaxial source/drain region having a convex top surface;
growing a second epitaxial source/drain region in the second fin and on the second fin spacers, the second epitaxial source/drain region having a second width, the first width being less than the second width, the second epitaxial source/drain region having a concave top surface;
and
depositing a dielectric material on the convex top surface of the first epitaxial source/drain region and on the concave top surface of the second epitaxial source/drain region.

6 more elements

A device comprising:

a first fin extending from a substrate;
a second fin extending from the substrate;
a first fin spacer on a first sidewall of the first fin, the first fin spacer having a first spacer height;
a second fin spacer on a second sidewall of the second fin, the second fin spacer having a second spacer height, the first spacer height being greater than the second spacer height;
a first epitaxial source/drain region on the first fin spacer and in the first fin, the first epitaxial source/drain region having a first width, the first epitaxial source/drain region having a convex top surface;
and
a second epitaxial source/drain region on the second fin spacer and in the second fin, the second epitaxial source/drain region having a second width, the first width being greater than the second width, the second epitaxial source/drain region having a concave top surface, the first epitaxial source/drain region having a same number of semiconductor material layers as the second epitaxial source/drain region.

4 more elements

A device comprising:

a first fin extending from a substrate;
a second fin extending from the substrate;
a first epitaxial source/drain region in the first fin, the first epitaxial source/drain region having a first width, the first epitaxial source/drain region having a convex top surface, the convex top surface raised above a first top surface of the first fin;
a second epitaxial source/drain region in the second fin, the second epitaxial source/drain region having a second width, the first width being greater than the second width, the second epitaxial source/drain region having a concave top surface, the concave top surface raised above a second top surface of the second fin;
first fin spacers on first sidewalls of the first epitaxial source/drain region and the first fin, the first fin spacers having a first spacer height;
and
second fin spacers on second sidewalls of the second epitaxial source/drain region and the second fin, the second fin spacers having a second spacer height, the first spacer height being greater than the second spacer height.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/068,075Filed 19 Dec 2022 · continuation
Priority: 14 Aug 2020
Published: US 2023/0123868 A120 Apr 2023
Granted: 4 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
H10D 62/151
Source or drain regions of field-effect devices: of igfets

Family

Application63/065,552Us provisional application · filed 14 Aug 2020
Application63/082,526Us provisional application · filed 24 Sep 2020
Application17/155,690Parent of this continuation · filed 22 Jan 2021
US 2023/0123868 A1Pre-grant publication · published 20 Apr 2023
US 11,532,520 B2Parent of this continuation
US 2022/0051949 A1Published application
US 12,002,717 B2This patent

From the US filing history. Foreign family members aren’t listed.

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