Phase control in contact formation

A method comprising:

• forming a first metallic feature, wherein the first metallic feature comprises a gate electrode or a source/drain contact plug of a transistor;
• forming an etch stop layer over the first metal feature;
• forming a dielectric layer over the etch stop layer;
• etching the dielectric layer and the etch stop layer to form an opening, with the first metallic feature exposed to the opening, wherein the opening has a first width;
• etching the first metallic feature to form an opening extension underlying and joined to the opening, wherein the opening extension has a second width greater than the first width;
• oxidizing a surface layer of the first metallic feature to form a metal oxide layer at a surface of the first metallic feature, wherein at a time the surface layer starts to be oxidized, a top surface of the dielectric layer is exposed;
• performing a reduction reaction to reduce the metal oxide layer back to an elemental metal;
• and
• performing a bottom-up deposition process to deposit a tungsten plug in the opening.

An integrated circuit device comprising:

• a first metallic feature comprising a first portion and a second portion over the first portion, wherein the second portion comprises an element selected from the group consisting essentially of silicon, boron, phosphorus, arsenic, and combinations thereof, and the first portion is free from the element;
• a dielectric layer over the first metallic feature;
• and
• a second metallic feature over the first metallic feature and having a portion in the dielectric layer, wherein the second metallic feature comprises a third portion and a fourth portion over the third portion, with the third portion over and contacting the second portion to form an interface therebetween, and wherein the third portion comprises the element, and the fourth portion is free from the element.