Semiconductor manufacturing chamber with plasma/gas flow control device

A method for processing a semiconductor wafer secured to a mounting platform housed in a process chamber, said method comprising:

• via an inlet port, introducing a process gas into the process chamber;
• exciting the introduced process gas within the process chamber into a plasma by energizing a first electrode;
• and
• controlling a flow of the introduced process gas using an annular plate having a plurality of perforations therein, said annular plate being housed within the process chamber;
• wherein:
• the annular plate encircles an outer edge of the semiconductor wafer when the semiconductor wafer is secured to the mounting platform;
• the annular plate has a first edge at a first end thereof and a second edge at a second end thereof, said first end being opposite the second end;
• the first end resides in a first plane and the second end resides in a second plane different from the first plane, said first plane being located above the second plane and below or coplanar with the semiconductor wafer when the semiconductor wafer is secured to the mounting platform;
• and
• the first edge has a first radius measured from a central axis of the annular plate and the second edge has a second radius measured from the central axis, said second radius being greater than the first radius.

A method for exposing a semiconductor wafer held in a process chamber to a plasma, said method comprising:

• providing a process gas to the process chamber, said process gas being selectively excited into the plasma to which the semiconductor wafer is exposed;
• using a radio frequency generator, selectively energizing an electrode to selectively excite the process gas within the process chamber;
• and
• controlling flow of the process gas provided to the process chamber using a control ring that surrounds a region within the process chamber where the semiconductor wafer is held, said control ring comprising a perforated annular surface extending between a first edge and a second edge;
• wherein:
• the first edge resides in a first plane and the second edge resides in a second plane different from and not co-planar with the first plane, said first plane being located above the second plane and below or coplanar with the semiconductor wafer;
• and
• the annular surface is inclined between the first and second planes;
• and
• the first edge has a first radius measured from a central axis of the annular plate and the second edge has a second radius measured from the central axis, said second radius being greater than the first radius.