Voltage waveform generator, wafer processing apparatus and plasma processing apparatus
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunbae Kim, Hyejin Kim, Chanhee Park
Life of this patent
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Abstract
A wafer processing apparatus includes a chamber, and a voltage waveform generator configured to accelerate plasma ions of the chamber, the voltage waveform generator includes: a pulse circuit configured to apply a chamber voltage, which is a pulse voltage, to the chamber by adjusting a chamber current applied to the chamber; and a slope circuit configured to generate a slope in an on-duty of the chamber voltage, which is the pulse voltage, and the pulse circuit includes a first inductive element configured to store a first internal current.
Claims20
A wafer processing apparatus comprising:
- a chamber configured to load a wafer;
- a radio frequency (RF) power source configured to generate plasma ions in the chamber;
- and
- a voltage waveform generator configured to accelerate the plasma ions toward the wafer,
- wherein the voltage waveform generator comprises:
- a pulse circuit comprising a first inductive element configured to store a first internal current, the pulse circuit being configured to apply a pulse voltage to the chamber by adjusting a chamber current applied to the chamber;
- and
- a slope circuit configured to generate a slope in an on-duty of the pulse voltage,
- wherein the pulse circuit and the slope circuit are electrically connected in parallel to an input terminal of the chamber, and
- wherein the pulse circuit comprises a first current discharging circuit comprising:
- a first switch, a first diode, a second switch and a second diode arranged in series in a first path configured to allow the first internal current to enter a first terminal of the chamber, and
- a third switch, a third diode, a fourth switch and a fourth diode arranged in series in a second path configured to allow the first internal current to enter a second terminal of the chamber opposite to the first terminal.
A plasma processing apparatus comprising:
- a chamber in which a plasma process is performed;
- and
- a voltage waveform generator configured to apply a non-sinusoidal periodic wave voltage to the chamber,
- wherein the voltage waveform generator comprises:
- a pulse circuit configured to apply a pulse voltage to the chamber by applying a first output current to the chamber;
- and
- a slope circuit configured to generate a slope in an on-duty of the pulse voltage, by applying a second output current to the chamber,
- wherein the pulse circuit and the slope circuit are electrically connected in parallel to an input terminal of the chamber,
- wherein the pulse circuit comprises a first current discharging circuit comprising:
- a first switch, a first diode, a second switch and a second diode arranged in series in a first path configured to allow a first internal current to enter a first terminal of the chamber, and
- a third switch, a third diode, a fourth switch and a fourth diode arranged in series in a second path configured to allow the first internal current to enter a second terminal of the chamber opposite to the first terminal.
A plasma processing apparatus comprising
- a voltage waveform generator configured to apply a chamber voltage which is a non-sinusoidal periodic wave to a plasma chamber, wherein the voltage waveform generator comprises:
- a pulse circuit comprising a first inductive element configured to store a first internal current;
- and
- a slope circuit comprising a second inductive element configured to store a second internal current,
- wherein the pulse circuit is configured to apply the first internal current to the plasma chamber to generate a pulse in the chamber voltage, and the slope circuit is configured to apply the second internal current to the plasma chamber to generate a slope in an on-duty of the pulse
- wherein the pulse circuit and the slope circuit are electrically connected in parallel to an input terminal of the plasma chamber, and
- wherein the pulse circuit comprises a first current discharging circuit comprising:
- a first switch, a first diode, a second switch and a second diode arranged in series in a first path configured to allow the first internal current to enter a first terminal of the plasma chamber, and
- a third switch, a third diode, a fourth switch and a fourth diode arranged in series in a second path configured to allow the first internal current to enter a second terminal of the plasma chamber opposite to the first terminal.
Dependencies are inferred from the claim text.