Write circuit of memory device and method of operating the same
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Tsmc China Company Limited
InventorsXiu-Li Yang, Kuan Cheng, He-Zhou Wan, Wei-Yang Jiang
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Abstract
A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.
Claims20
A device, comprising:
- a data latch configured to receive a first clock signal and a second clock signal, and generate a write signal according to a write data signal inputted to the data latch;
- a first logic element configured to generate the second clock signal based on the first clock signal;
- a second logic element configured to generate the first clock signal based on a third clock signal and a fourth clock signal that are different from each other;
- and
- a plurality of memory banks configured to operate according to the write signal, the third clock signal and the fourth clock signal.
A method, comprising:
- generating a first global write signal based on a first clock signal and a write data signal;
- driving a first memory bank by the first global write signal;
- generating a second global write signal based on a second clock signal and the write data signal;
- driving a second memory bank by the second global write signal;
- generating a third global write signal based on a third clock signal and the write data signal;
- and
- driving a third memory bank by the third global write signal,
- wherein the first clock signal, the second clock signal and the third clock signal are different from each other, and
- the first memory bank, the second memory bank and the third memory bank are different from each other.
A method, comprising:
- generating a write signal according to a write data signal inputted to a data latch, a first clock signal and a second clock signal;
- generating the second clock signal based on the first clock signal;
- generating the first clock signal based on a third clock signal and a fourth clock signal;
- and
- operating a plurality of memory banks according to the write signal, the third clock signal and the fourth clock signal,
- wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are different from each other.
Dependencies are inferred from the claim text.