Read clock toggle at configurable PAM levels

A method for selectively providing a read clock signal from a memory to a memory controller over a memory bus, the method comprising:

• deactivating a pulse-amplitude modulation (PAM) driver, capable of driving at least three levels indicating respective digital values, for a read clock signal following a memory read;
• responsive to a new memory read, activating the PAM driver and providing a preamble signal for a read clock signal, the preamble signal including, in order, at least one static state, an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate;
• determining a length of at least the initial toggling state and the final toggling state based on values in mode register;
• and
• following the preamble, toggling the PAM driver at the second rate to provide the read clock signal.

A data processing system comprising:

• at least one processor;
• a memory controller coupled to the processor over a memory bus;
• and
• a dynamic random-access memory (DRAM) coupled to the memory controller over a memory bus, the DRAM including read clock (strobe) circuit for selectively providing a read clock signal from a memory to the memory controller over the memory bus, comprising:
• a pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values;
• a mode register;
• and
• and a digital control circuit coupled to the input of the PAM driver, the digital control circuit operable to cause the PAM driver to selectively provide the read clock signal during a read operation, and to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including, an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, and
• wherein a length of the initial toggling state and a length of the final toggling state are based on values in the mode register.