On-die termination of address and command signals
AssigneeRambus Inc.
InventorsIan Shaeffer, Kyung Suk Oh
Life of this patent
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Abstract
A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.
Claims20
A memory controller to control the operation of a memory device, the memory controller comprising:
- a command/address (CA) transmission circuit;
- the memory controller to:
- send, using the CA transmission circuit, command/address (CA) signals via a CA bus to respective inputs of the memory device and a chip select signal to a chip select input of the memory device;
- and
- send to the memory device:
- register values, for storage in a plurality of registers of the memory device, including a register value that selects from two or more impedance values of on-die termination (ODT) impedances to apply to each of the respective inputs of the memory device that receive the CA signals;
- wherein the register values include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals, and a register value that selectively enables application of a CS ODT impedance to the chip select input.
A method of operation of a memory controller for controlling a memory device, the method comprising:
- sending, from the memory controller, command/address (CA) signals to respective inputs of the memory device;
- and
- sending, from the memory controller to the memory device:
- register values, for storage in a plurality of registers of the memory device, wherein the register values represent two or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals;
- wherein the register values sent by the memory controller for storage in the plurality of registers of the memory device include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.
A memory controller to control the operation of a memory device, the memory controller comprising:
- a circuit to drive command and address signals;
- and
- a first circuit to drive a chip select (CS) signal;
- the memory controller is configured to:
- send, using the circuit to drive command and address signals, command/address (CA) signals to respective inputs of the memory device and, using the first circuit, the CS signal to a chip select input of the memory device;
- and
- send to the memory device:
- register values, for storage in a plurality of registers in the memory device, wherein the register values include:
- values representing two or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals;
- and
- a value for enabling application of one of a plurality of CS ODT impedance values to the chip select input of the memory device;
- wherein the register values sent by the memory controller for storage in the plurality of registers in the memory device include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.
Dependencies are inferred from the claim text.