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US 12,002,538 B2Granted
Memory device with data mergers and aligner
OwnerYoung Seung Kim, Seung Moon Yoo +1inventors
InventorsYoung Seung Kim, Seung Moon Yoo, Min Chul Jung
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Abstract
A memory device may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and an aligner that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data.
Claims11
A memory device comprising:
- a memory cell array in which memory cells are connected to word lines and bit lines in a matrix form;
- a plurality of mergers connected in series to transmit data that is read from a selected memory cell from among the memory cells included in the memory cell array and transformed into one of a direct current form and a pulse form;
- and
- an aligner configured to delay an edge of first output data output by one of the plurality of mergers in synchronization with an edge of a control pulse, wherein first data which is one of data bit ‘0’ and data bit ‘1’ is input to the merger in the direct current form of first logic and second data which is the other of the data bit ‘0’ and the data bit ‘1’ is input to the merger in the pulse form in which the first logic is changed through second logic back to the first logic.
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Dependencies are inferred from the claim text.