Pre-decoder circuity

A method of operating memory, comprising:

• providing a first positive configuration pre-decoded address signal to a gate of a first transistor of pre-decoder circuitry, wherein the first positive configuration pre-decoded address signal has a high voltage value or a low voltage value;
• providing a second positive configuration pre-decoded address signal to a gate of a second transistor of the pre-decoder circuitry, wherein the second positive configuration pre-decoded address signal has the high voltage value or the low voltage value;
• and
• providing a positive configuration de-selection bias condition for a first gate of a first n-type transistor of decoder circuitry and a second gate of a second n-type transistor of the decoder circuitry when the first positive configuration pre-decoded address signal has the low voltage value or when the second positive configuration pre-decoded address signal has the low voltage value.

A method of operating memory, comprising:

• providing a first negative configuration pre-decoded address signal to a gate of a first transistor of pre-decoder circuitry, wherein the first negative configuration pre-decoded address signal has a high voltage value or a low voltage value;
• providing a second negative configuration pre-decoded address signal to a gate of a second transistor of the pre-decoder circuitry, wherein the second negative configuration pre-decoded address signal has the high voltage value or the low voltage value;
• and
• providing a negative configuration de-selection bias condition for a first gate of a first n-type transistor of decoder circuitry and a second gate of a second n-type transistor of the decoder circuitry when the first negative configuration pre-decoded address signal has the low voltage value or when the second negative configuration pre-decoded address signal has the low voltage value.

An apparatus, comprising:

• a memory array including a plurality of memory cells;
• and
• decoder circuitry coupled to the array of memory cells, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate;
• and
• pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the pre-decoder circuitry includes a decoding portion, a first level shift portion, and a second level shift portion, wherein:
• a gate of a first transistor of the decoding portion is configured to receive a first pre-decoded address signal having a pre-decoded high voltage value relative to a pre-decoded low voltage value;
• a gate of a second transistor of the decoding portion is configured to receive a second pre-decoded address signal having the pre-decoded high voltage value;
• the first level shift portion is configured to increase the pre-decoded high voltage value to provide a positive voltage for the first gate;
• the second level shift portion is configured to decrease the pre-decoded high voltage value to provide a negative voltage for the second gate,
• wherein the bias condition provides a selection signal for a positive configuration for the array of memory cells.