Semiconductor device comprising memory cell array and arithmetic circuit

A semiconductor device comprising:

• a memory cell array;
• a sense amplifier circuit;
• and
• an arithmetic circuit,
• wherein a first signal is input to the semiconductor device,
• wherein the memory cell array comprises m×n memory cells and at least n wirings,
• wherein m and n are each an integer of 2 or more,
• wherein the m×n memory cells are arranged in a matrix,
• wherein the sense amplifier circuit comprises at least n first circuits,
• wherein each of the n wirings is electrically connected to m of the memory cells,
• wherein the n wirings are electrically connected to the n first circuits,
• wherein the arithmetic circuit comprises s second circuits,
• wherein s is an integer of 1 or more and n or less,
• wherein the second circuit is electrically connected to t of the first circuits,
• wherein t is an integer of 1 or more and s×t is an integer of n or less,
• wherein a second signal of a weight coefficient is input from the first circuit to each of the second circuits,
• wherein the second circuit performs an arithmetic operation using the first signal and the second signal, and
• wherein the s second circuits perform parallel arithmetic operations.

A semiconductor device comprising:

• a memory cell array;
• a sense amplifier circuit,
• a multiplexer circuit, and
• an arithmetic circuit,
• wherein the memory cell array comprises m×n memory cells and at least n wirings,
• wherein m and n are each an integer of 2 or more,
• wherein the m×n memory cells are arranged in a matrix,
• wherein the sense amplifier circuit comprises at least n first circuits,
• wherein each of the n wirings is electrically connected to m of the memory cells,
• wherein the n wirings are electrically connected to the n first circuits,
• wherein the multiplexer circuit has a function of selecting s wirings from the n wirings and electrically connecting the first circuits electrically connected to the s wirings and the arithmetic circuit,
• wherein s is an integer of 1 or more and n or less,
• wherein the arithmetic circuit comprises t second circuits,
• wherein t is an integer of 1 or more and s or less,
• wherein the second circuit is electrically connected to u of the first circuits,
• wherein u is an integer of 1 or more and t×u is an integer of s or less,
• wherein the second circuit performs an arithmetic operation using a signal of a weight coefficient output from the first circuit, and
• wherein the s second circuits perform parallel arithmetic operations.