Memory array word line routing

A method comprising:

• patterning a conductive layer in a multi-layer stack to form a word line and a first trench adjacent the word line;
• depositing a ferroelectric (FE) material in the first trench;
• depositing an oxide semiconductor (OS) layer in the first trench and on the FE material;
• patterning the OS layer to form a second trench exposing the FE material;
• forming a dielectric material in the second trench;
• patterning the dielectric material and the FE material to form a third trench;
• forming a first contact in the third trench;
• and
• forming a first conductive line electrically coupled to the first contact and the word line.

A method comprising:

• forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating conductive layers and dielectric layers;
• patterning a first trench extending through the multi-layer stack;
• depositing a ferroelectric (FE) material along sidewalls and a bottom surface of the first trench;
• depositing an oxide semiconductor (OS) layer over the FE material;
• depositing a dielectric material over the FE material;
• forming an inter-metal dielectric (IMD) over the multi-layer stack;
• forming a first conductive contact extending through the IMD to a first conductive layer of the multi-layer stack, wherein the first conductive contact is electrically coupled to the first conductive layer;
• forming a second conductive contact extending through the dielectric material and the FE material;
• and
• forming a conductive line electrically coupling the second conductive contact with the first conductive contact.