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US 12,002,529 B2Granted
Shift register, semiconductor device, display device, and electronic device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorAtsushi Umezaki
Life of this patent
Estimating the term…
Abstract
In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.
Claims4
A display device comprising:
- a gate driver comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
- and
- a pixel comprising an eighth transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate signal line,
- wherein the other of the source and the drain of the first transistor is electrically connected to a clock signal line,
- wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate signal line,
- wherein the other of the source and the drain of the second transistor is electrically connected to a first power source line,
- wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,
- wherein the other of the source and the drain of the third transistor is electrically connected to a second power source line,
- wherein a gate of the third transistor is electrically connected to a first wiring to which a start pulse is input,
- wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
- wherein the other of the source and the drain of the fourth transistor is electrically connected to a third power source line,
- wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
- wherein the other of the source and the drain of the fifth transistor is electrically connected to the third power source line,
- wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
- wherein the other of the source and the drain of the sixth transistor is electrically connected to a second wiring,
- wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,
- wherein the other of the source and the drain of the seventh transistor is electrically connected to the third power source line,
- wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor, and
- wherein a gate of the eighth transistor is electrically connected to the gate signal line.
18 more elements
A display device comprising:
- a gate driver comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
- and
- a pixel comprising an eighth transistor,
- wherein one of a source and a drain of the first transistor is directly connected to a gate signal line,
- wherein the other of the source and the drain of the first transistor is directly connected to a clock signal line,
- wherein a gate of the first transistor is directly connected to one of a source and a drain of the third transistor,
- wherein one of a source and a drain of the second transistor is directly connected to the gate signal line,
- wherein the other of the source and the drain of the second transistor is directly connected to a first power source line,
- wherein a gate of the second transistor is directly connected to a gate of the fourth transistor,
- wherein the other of the source and the drain of the third transistor is directly connected to a second power source line,
- wherein a gate of the third transistor is directly connected to a first wiring to which a start pulse is input,
- wherein one of a source and a drain of the fourth transistor is directly connected to the gate of the first transistor,
- wherein the other of the source and the drain of the fourth transistor is directly connected to a third power source line,
- wherein one of a source and a drain of the fifth transistor is directly connected to the gate of the first transistor,
- wherein the other of the source and the drain of the fifth transistor is directly connected to the third power source line,
- wherein a gate of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor,
- wherein the other of the source and the drain of the sixth transistor is directly connected to a second wiring,
- wherein a gate of the sixth transistor is directly connected to one of a source and a drain of the seventh transistor,
- wherein the other of the source and the drain of the seventh transistor is directly connected to the third power source line,
- wherein a gate of the seventh transistor is directly connected to the gate of the first transistor, and
- wherein a gate of the eighth transistor is directly connected to the gate signal line.
18 more elements
Dependencies are inferred from the claim text.