Defect detection during program verify in a memory sub-system

A method comprising:

• sampling a load current from a selected wordline of a plurality of wordlines of a memory array of a memory device during a program verify phase of a program operation associated with the selected wordline;
• generating a measured output voltage that modulates with respect to the load current;
• performing a comparison of the measured output voltage to a reference voltage;
• and
• identifying a presence of a defect on the selected wordline in view of the comparison of the measured output voltage to the reference voltage.

A memory device comprising:

• a memory array comprising a plurality of wordlines;
• a defect detector component operatively coupled with the memory array, to perform operations comprising:
• sampling a load current from a selected wordline of the plurality of wordlines of the memory array during a program verify phase of a program operation associated with the selected wordline;
• generating a measured output voltage that modulates with respect to the load current;
• and
• performing a comparison of the measured output voltage to a reference voltage;
• and
• control logic, operatively coupled with the memory array and the defect detector component, to perform operations comprising:
• identifying a presence of a defect on the selected wordline in view of the comparison of the measured output voltage to the reference voltage.