Methods and apparatus for NAND flash memory

A method for programming multiple-level cells in a memory array, wherein the memory array comprises a plurality of planes, and wherein each plane comprises a plurality of bit lines, the method comprising:

• storing multiple data bits in a first group of planes, one data bit per plane, wherein the multiple data bits are stored in bit line capacitances of the first group of planes, and wherein the first group of planes is coupled to a first group of page buffers, respectively;
• programming a selected multiple-level cell in a selected plane according to the multiple data bits that are stored in the bit line capacitances of the first group of planes, and wherein the selected plane is not one of the first group of planes;
• and
• latching the multiple data bits that are stored in the bit line capacitances of the first group of planes into data latches of the first group of page buffers.