Sequential wordline erase verify schemes

A memory device comprising:

• a memory array comprising a plurality of wordline groups, wherein each wordline group of the plurality of wordline groups comprises a set of even wordlines and a set of odd wordlines;
• and
• control logic, operatively coupled with the memory array, to perform operations comprising:
• causing an erase verify of an erase verify process to be performed sequentially with respect to each wordline group of the plurality of wordline groups;
• determining whether each wordline group of the set of wordline groups has passed the erase verify;
• and
• in response to determining that each wordline group has passed the erase verify, causing the erase verify process to terminate.

A method comprising:

• identifying, by processing device from a plurality of wordline groups, a set of passing wordline groups and a set of failing wordline groups, wherein each wordline group of the plurality of wordline groups comprises a set of even wordlines and a set of odd wordlines, wherein the set of passing wordline groups comprises at least one passing wordline group determined to have passed a first erase verify of an erase verify process, and wherein the set of failing wordline groups comprises at least one failing wordline group determined to have failed the first erase verify;
• causing, by the processing device, an inhibiting bias voltage to be applied with respect to each passing wordline group of the set of passing wordline groups;
• and
• causing, by the processing device, a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.