Memory circuit, system and method for rapid retrieval of data sets
AssigneeSunrise Memory Corporation
InventorEli Harari
Life of this patent
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Abstract
A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.
Claims26
A 3-dimensional array of NOR memory strings each comprising a plurality of thin-film storage transistors, the 3-dimensional array comprising first and second groups of data pages, each data page having a predetermined number of storage transistors that are programmed, erased, or read simultaneously, wherein each data page in the second group stores resource management data relating to data in one or more corresponding data pages of the first group, and wherein the resource management data in each data page of the second group is stored or updated in conjunction with programming, erasing or reading of data in each corresponding page of the first group.
A memory circuit formed on a semiconductor substrate that has a substantially planar surface and that includes circuitry formed therein and thereon, the memory circuit comprising a plurality of storage transistors formed over the planar surface, being organized as a plurality of NOR memory strings, each NOR memory string comprising:
- (i) a source region and a drain region, each extending along a first direction that is substantially parallel the planar surface;
- (ii) a dielectric layer, also extending along the first direction, provided between the source region and the drain region and electrically isolating the source region from the drain region;
- (iii) a plurality of channel regions, each channel region being provided over the dielectric layer and in electrical contact with both the source region and the drain region;
- (iv) a data storage layer provided over the source region, the drain region and the channel regions;
- and
- (v) a plurality of conductors, each provided next to an associated one of the channel region but separated therefrom by an associated portion of the data storage layer, such that each conductor, serving as a gate electrode, the associated portion of the storage layer, the associated channel region, the source region and the drain region form one of the thin-film storage transistors of the NOR memory string;
- wherein one or more voltage sources are formed in the semiconductor substrate for biasing the thin-film transistors of the NOR memory string during a memory operation, and wherein the source region and the drain region each comprise doped semiconductor material, each NOR memory string further comprising a dopant diffusion-blocking layer between the channel regions and one or both of the source region and the drain region.
Dependencies are inferred from the claim text.