Memory device and operation method thereof

A memory device including:

• a plurality of bit lines,
• a plurality of ground select lines, a plurality of first switches being on intersection of the bit lines and the ground select lines;
• a plurality of string select lines, a plurality of second switches being on intersection of the bit lines and the string select lines;
• a plurality of word lines, a plurality of memory cells being on intersection of the bit lines and the word lines;
• and
• a plurality of dummy word lines, a plurality of dummy memory cells being on intersection of the bit lines and the dummy word lines;
• wherein
• a first part of the dummy word lines are adjacent the string select lines;
• a second part of the dummy word lines are adjacent the ground select lines;
• the word lines are between the first part of the dummy word lines and the second part of the dummy word lines;
• a plurality of threshold voltages of a plurality of switches on the string select lines and the ground select lines are programmed to have a first reference threshold voltage, and
• a plurality of threshold voltages of the dummy memory cells on the dummy word lines are programmed, each of the plurality of threshold voltages of the dummy memory cells on the dummy word lines gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells are higher than the first reference threshold voltage;
• wherein the first direction being from the string select lines to the word lines and the second direction being from the ground select lines to the word lines.