Memory device performing temperature compensation and operating method thereof

A page buffer of a memory device, wherein the page buffer is arranged to correspond to a first bit line of a plurality of bit lines of the memory device, and comprises:

• a first latch configured to latch data based on a voltage level of a first sensing node of the page buffer;
• a shut off transistor connected to the first bit line and configured to operate based on a shut-off control signal;
• a bit line connection transistor arranged between the shut off transistor and the first sensing node and configured to operate based on a bit line connection control signal;
• a bit line clamping transistor arranged between a first node and a power supply voltage, wherein the bit line clamping transistor is configured to operate based on a bit line clamping control signal, and the first node is arranged between the shut off transistor and the bit line connection transistor;
• and
• a trip control transistor arranged between the first latch and the first sensing node, and configured to operate based on a trip control voltage,
• wherein the page buffer is configured to control, as a temperature of the memory device decreases, a level of any one or any combination of the shut-off control signal, the bit line connection control signal, and the bit line clamping control signal to increase, and
• wherein the page buffer is configured to control, as the level of the trip control voltage increases, a sensing trip level of the page buffer to increase.

A memory device comprising:

• a memory cell array comprising a plurality of memory cells;
• a page buffer circuit connected to the memory cell array through a plurality of bit lines and comprising a page buffer connected to one of the plurality of bit lines, the page buffer comprising at least one first latch configured to store data based on a voltage level of a sensing node;
• and
• a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit,
• wherein the page buffer further comprises one or more transistors connected between a corresponding bit line and the sensing node, and a trip control transistor arranged between the sensing node and the at least one first latch, and
• wherein the control circuit is further configured to, as a temperature of the memory device decreases, control a level of a trip control voltage applied to a gate of the trip control transistor to increase.