Semiconductor memory device
AssigneeSK hynix Inc.
InventorHee Youl Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells through a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control an operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external power voltage terminal, and an internal operation circuit coupled to the first node.
Claims14
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells for storing data;
- a page buffer coupled to at least one memory cell among the plurality of memory cells through a bit line and configured to store data in the at least one memory cell;
- and
- control logic configured to control an operation of the page buffer,
- wherein the page buffer comprises:
- a first transistor coupled between the bit line and a first node;
- a second transistor coupled between the bit line and an external power voltage terminal;
- and
- an internal operation circuit coupled to the first node,
- wherein the control logic is configured to:
- control, when a program inhibit bias is transmitted to the bit line, the page buffer to transmit the program inhibit bias from the internal operation circuit to the bit line by turning on the first transistor and disconnect between the external power voltage terminal and the bit line by turning off the second transistor;
- and
- apply, to suppress occurrence of a leakage current from a side of the bit line to a side of the second transistor, a first voltage greater than 0V to the external power voltage terminal while the program inhibit bias is transmitted to the bit line during a program operation.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells for storing data;
- a page buffer coupled to at least one memory cell among the plurality of memory cells through a bit line and configured to erase data stored in the at least one memory cell;
- and
- control logic configured to control an operation of the page buffer,
- wherein the page buffer comprises:
- a first transistor coupled between the bit line and a first node;
- a second transistor coupled between the first node and a ground;
- a third transistor coupled between the bit line and an external power voltage terminal;
- and
- an internal operation circuit coupled to the first node,
- wherein the control logic is configured to:
- apply, when an erase bias is applied to the bit line, an erase voltage to the external power voltage terminal;
- control the page buffer to connect the external power voltage terminal and the bit line by turning on the third transistor;
- and
- apply, to increase a breakdown voltage in a junction overlap region of the first transistor, a first voltage greater than 0V and less than a turn-on voltage to a gate of the first transistor while the erase voltage is applied to the bit line through the external power voltage terminal during an erase operation.
Dependencies are inferred from the claim text.