Memory device configured to apply different erase intensities to different blocks during an erase operation and memory system for instructing the memory device to carry out the erase operation

A memory system comprising:

• a memory device;
• and
• a memory controller configured to instruct the memory device to erase data in the memory device,
• wherein the memory device includes
• a first block including a first memory cell and a first word line connected to the first memory cell;
• a second block including a second memory cell and a second word line connected to the second memory cell;
• and
• a control circuit configured to execute an erase sequence for the first and second blocks, and determine voltages to be applied to the first and second word lines during the erase sequence, wherein the control circuit
• applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation of a first erase sequence is executed on the first and second blocks, and
• applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation of a second erase sequence is executed on the first and second blocks.