Memory device and refresh method thereof

A memory device comprising:

• a memory cell array comprising a plurality of rows;
• and
• a refresh control circuit comprising:
• a plurality of registers each configured to store a row address;
• a plurality of counters respectively corresponding to the plurality of registers, and each configured to count a number of hits in a corresponding register among the plurality of registers;
• a first control circuit configured to selectively enable a replacement control signal based on a replacement probability;
• a second control circuit configured to, based on an incoming row address indicating a hit register among the plurality of registers, store the incoming row address to the hit register, and to, based on each of the plurality of registers storing a row address that does not correspond to the incoming row address and the replacement control signal being enabled, replace a first row address stored in a first register among the plurality of registers with the incoming row address;
• and
• a calculator configured to identify a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.

A refresh method of a memory device including a memory cell array including a plurality of rows and a refresh control circuit including a plurality of registers, the refresh method comprising:

• receiving an incoming row address;
• determining whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address;
• maintaining the first row address stored in the first register or replacing the first row address stored in the first register with the incoming row address based on a result of the determining;
• determining a victim row address based on a second row address stored in a second register of the plurality of registers;
• and
• refreshing a victim row indicated by the victim row address.