Using split word lines and switches for reducing capacitive loading on a memory system

A memory system comprising:

• a memory array including:
• a first set of memory cells including a first string of memory cells having gate electrodes, each gate electrode coupled to a respective first word line;
• a second string of memory cells having gate electrodes, each gate electrode coupled to a respective second word line;
• a first switch;
• a first line coupling a first electrode of the first switch to first electrodes of the first string of memory cells;
• a second line coupling the first electrodes of the first string of memory cells to first electrodes of the second string of memory cells, the second line distinct from and coupling to the first line;
• a third line coupling second electrodes of the second string of memory cells;
• a fourth line coupling the second electrodes of the second string of memory cells to second electrodes of the first string of memory cells, the third line distinct from and coupled to the fourth line, the third line and the fourth line separate from the first line and the second line;
• and
• a controller coupled to the memory array, the controller is to:
• toggle the first switch to electrically couple a first global bit line to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells;
• and
• configure, responsive to toggling the first switch, the first string of memory cells using the first word line.

A method comprising:

• coupling, during a first time period, first electrodes of a first set of memory cells to a first global bit line, wherein the first set of memory cells includes a first routing line, a first string of memory cells, a second routing line, and a second string of memory cells, wherein the first routing line is coupled between the first global bit line and the first electrodes of the first string of memory cells, wherein the second routing line is coupled between the first electrodes of the first string of memory cells and the first electrodes of the second string of memory cells, wherein the first routing line is distinct from and coupling to the second routing line;
• coupling, during the first time period, second electrodes of the first set of memory cells to a first global select line, wherein the first set of memory cells further includes a third routing line and a fourth routing line, wherein the third routing line is coupled between the global select line and second electrodes of the first string of memory cells, wherein the fourth routing line is coupled between second electrodes of the first string of memory cells and second electrodes of the second string of memory cells, wherein the third routing line is distinct from and coupling to the fourth routing line, and wherein the third routing line and the fourth routing line are separate from the first routing line and the second routing line;
• decoupling, during the first time period, first electrodes of a second set of memory cells from the first global select line;
• decoupling, during the first time period, second electrodes of the second set of memory cells from the first global bit line;
• and
• accessing, during the first time period, a gate electrode of the first string of memory cells of the first set of memory cells without accessing a gate electrode of the second string of memory cells of the first set of memory cells.