Shift register circuit including denoising control sub-circuit and method for driving same, and gate driving circuit and display apparatus

A shift register circuit, comprising:

• a first transistor, a control electrode of the first transistor being coupled to a first clock signal terminal, a first electrode of the first transistor being coupled to a first voltage terminal, and a second electrode of the first transistor being coupled to a second denoising control node;
• a first capacitor, a first terminal of the first capacitor being coupled to a second electrode of a fifth transistor, and a second terminal of the first capacitor being coupled to the second denoising control node;
• the fifth transistor, a control electrode of the fifth transistor being coupled to the scan signal output terminal, and a first electrode of the fifth transistor being coupled to the second clock signal terminal,
• a second transistor, a control electrode of the second transistor being coupled to the second denoising control node, a first electrode of the second transistor being coupled to a first denoising control node, and a second electrode of the second transistor being coupled to the second denoising control node;
• a second capacitor, a first terminal of the second capacitor being coupled to a first signal terminal, and a second terminal of the second capacitor being coupled to the first denoising control node;
• and
• a sixth transistor, a control electrode of the sixth transistor being coupled to the first denoising control node, a first electrode of the sixth transistor being coupled to the first voltage terminal, and a second electrode of the sixth transistor being coupled to a scan signal output terminal.

A shift register circuit, comprising

• a denoising control sub-circuit, a denoising sub-circuit, an input sub-circuit and an output sub-circuit;
• wherein the denoising control sub-circuit is coupled to a first voltage terminal, a first clock signal terminal, a second clock signal terminal and a first denoising control node;
• and
• the denoising control sub-circuit is configured to:
• generate an alternating voltage signal according to a voltage of the first voltage terminal and a signal of the second clock signal terminal in response to a signal of the first clock signal terminal;
• rectify the alternating voltage signal;
• and
• output a signal to the first denoising control node, so that a voltage of the first denoising control node is maintained to be a voltage that enables the denoising sub-circuit to be turned on;
• the denoising control sub-circuit is further coupled to a cascade signal output terminal and a second signal terminal;
• and
• the denoising control sub-circuit is further configured to control the denoising sub-circuit to be turned off according to a signal of the second signal terminal in response to a voltage of the cascade signal output terminal;
• the denoising sub-circuit is coupled to the first denoising control node and a scan signal output terminal;
• and
• the denoising sub-circuit is configured to denoise the scan signal output terminal in response to the voltage of the first denoising control node being the voltage that enables the denoising sub-circuit to be turned on;
• the input sub-circuit is coupled to the cascade signal output terminal and the output sub-circuit;
• the input sub-circuit is configured to control the voltage of the cascade signal output terminal;
• so as to enable the denoising sub-circuit to be turned on or turned off by the denoising control sub-circuit;
• and
• the input sub-circuit is further configured to transmit a turn-on signal to the output sub-circuit;
• and
• the output sub-circuit is further coupled to a fifth clock signal terminal and the scan signal output terminal;
• and
• the output sub-circuit is configured to transmit a signal of the fifth clock signal terminal to the scan signal output terminal in response to the turn-on signal transmitted by the input sub-circuit, wherein the output sub-circuit includes a fifteenth transistor, a control electrode of the fifteenth transistor is coupled to the output sub-circuit, a first electrode of the fifteenth transistor is coupled to the fifth clock signal terminal, and a second electrode of the fifteenth transistor is coupled to the scan signal output terminal.