Shift register, method for driving shift register, gate driving circuit and display panel

A gate driving circuit, comprising:

• a plurality of cascaded shift registers, comprising:
• a first output device, wherein a control terminal of the first output device is electrically connected to a first node, a first terminal of the first output device is electrically connected to a first clock signal terminal, and a second terminal of the first output device is electrically connected to an output terminal of the shift register;
• and
• a first node control device comprising a first switch device and a second switch device, wherein a control terminal of the first switch device is electrically connected to the first node, a first terminal of the first switch device is electrically connected to a first power supply voltage signal terminal, a second terminal of the first switch device is electrically connected to a second node;
• a control terminal of the second switch device is electrically connected to the second node, a first terminal of the second switch device is electrically connected to the first power supply voltage signal terminal, and a second terminal of the second switch device is electrically connected to the first node,
• wherein in a low level output phase, the first switch device is configured to be switched on under control of the first node and write a cut-off level of the first power supply voltage signal terminal into the second node, and the second switch device is configured to be switched off under control of the second node.

A display panel, comprising:

• a gate driving circuit, comprising:
• a plurality of cascaded shift registers, comprising:
• a first output device, wherein a control terminal of the first output device is electrically connected to a first node, a first terminal of the first output device is electrically connected to a first clock signal terminal, and a second terminal of the first output device is electrically connected to an output terminal of the shift register;
• and
• a first node control device comprising a first switch device and a second switch device, wherein a control terminal of the first switch device is electrically connected to the first node, a first terminal of the first switch device is electrically connected to a first power supply voltage signal terminal, a second terminal of the first switch device is electrically connected to a second node;
• a control terminal of the second switch device is electrically connected to the second node, a first terminal of the second switch device is electrically connected to the first power supply voltage signal terminal, and a second terminal of the second switch device is electrically connected to the first node,
• wherein in a low level output phase, the first switch device is configured to be switched on under control of the first node and write a cut-off level of the first power supply voltage signal terminal into the second node, and the second switch device is configured to be switched off under control of the second node.