Latch circuit for reducing noise based on center grayscale and data driver including the same
AssigneeLx Semicon Co., Ltd.
InventorsGi Baek Choi, Jong Hwi Park, Yong Jung Kwon, Jung Bae Yun
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Abstract
An embodiment provides a latch circuit which outputs, to a digital analog converter (DAC), a digital signal including grayscale data, the latch circuit including a first latch configured to store the digital signal and a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level, based on a center grayscale. The grayscale data includes first grayscale data and second grayscale data.
Claims20
A latch circuit outputting, to a digital analog converter (DAC), a digital signal comprising grayscale data, the latch circuit comprising:
- a first latch configured to store the digital signal;
- and
- a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level, based on a center grayscale,
- wherein the grayscale data comprises first grayscale data and second grayscale data,
- the first timing is timing at which the second grayscale data is applied by changing from the first grayscale data, and
- the first signal is a most significant bit (MSB) signal.
A data driver comprising:
- a digital analog converter (DAC) configured to convert, into an analog signal, a digital signal comprising grayscale data;
- and
- a latch circuit configured to transmit the digital signal to the DAC,
- wherein the latch circuit comprises:
- a first latch configured to store the digital signal;
- and
- a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level, based on a center grayscale,
- wherein the grayscale data comprises first grayscale data and second grayscale data,
- the first timing is timing at which the second grayscale data is applied by changing from the first grayscale data, and
- the first signal is a most significant bit (MSB) signal.
A latch circuit outputting, to a digital analog converter (DAC), a digital signal comprising grayscale data, the latch circuit comprising:
- a first latch configured to store the digital signal;
- and
- a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level and second timing at which a level of the first signal becomes a disable level,
- wherein the grayscale data comprises first grayscale data and second grayscale data,
- the first timing is timing at which the second grayscale data is applied by changing from the first grayscale data,
- the second timing is timing at which the first grayscale data is applied by changing from the second grayscale data, and
- the first signal is a most significant bit (MSB) signal.
A data driver comprising:
- a digital analog converter (DAC) configured to convert, into an analog signal, a digital signal comprising grayscale data;
- and
- a latch circuit configured to transmit the digital signal to the DAC,
- wherein the latch circuit comprises:
- a first latch configured to store the digital signal;
- and
- a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level and second timing at which a level of the first signal becomes a disable level,
- wherein the grayscale data comprises first grayscale data and second grayscale data,
- the first timing is timing at which the second grayscale data is applied by changing from the first grayscale data,
- the second timing is timing at which the first grayscale data is applied by changing from the second grayscale data, and
- the first signal is a most significant bit (MSB) signal.
Dependencies are inferred from the claim text.