US 12,001,844 B2Granted

Performance scaling for binary translation

AssigneeMicrosoft Technology Licensing, LLC

InventorsHee Jun Park, Mehmet Iyigun

Life of this patent

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Abstract

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

Claims20

Dependent claims

A system comprising:

a processor configured to execute instructions according to a first instruction set architecture (ISA);
and
memory coupled to the processor, the memory comprising computer executable instructions that, when executed by the processor, perform operations comprising:
varying an execution speed of an execution unit provided to the processor, based on a determination that the execution unit comprises a translated instruction or a native instruction, the varying the execution speed comprises:
based on the determination that the execution unit comprises a translated instruction, the translated instruction is executed using a high power-performance level that increases a default execution speed for the translated instruction, the translated instruction being an instruction translated from a second ISA to the first ISA;
and
based on the determination that the execution unit comprises a native instruction, the native instruction is executed using a low power-performance level that decreases a default execution speed for the native instruction, the native instruction being an instruction in the first ISA.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/185,122Filed 16 Mar 2023 · continuation
Priority: 2 Jun 2017
Published: US 2023/0333854 A119 Oct 2023
Granted: 4 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 9/30174
Runtime instruction translation, e.g. macros: for non-native instruction set, e.g. Javabyte, legacy code
G06F 8/52
Transformation of program code: binary to binary
G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction
G06F 9/30083
To perform miscellaneous control operations, e.g. NOP: power or thermal control instructions

Family

Application15/613,110Parent of this continuation · filed 2 Jun 2017
Application16/273,080Parent of this continuation · filed 11 Feb 2019
US 10,235,178 B2Parent of this continuation · filed 19 Mar 2019
Application16/714,626Parent of this continuation · filed 13 Dec 2019
US 10,732,975 B2Parent of this continuation · filed 4 Aug 2020
Application17/510,167Parent of this continuation · filed 25 Oct 2021
US 11,157,279 B2Parent of this continuation · filed 26 Oct 2021
US 2023/0333854 A1Pre-grant publication · published 19 Oct 2023
US 11,609,763 B2Parent of this continuation
US 2018/0349143 A1Published application
US 2019/0171458 A1Published application
US 2020/0117456 A1Published application
US 2022/0043656 A1Published application
US 12,001,844 B2This patent

From the US filing history. Foreign family members aren’t listed.

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