Hardware apparatuses and methods to switch shadow stack pointers

A method comprising:

• storing a current SSP for a current shadow stack in a shadow stack pointer (SSP) register;
• decoding an instruction to switch from the current shadow stack to a new shadow stack, the instruction having a memory operand providing a memory address of a token stored on the new shadow stack;
• and
• performing operations corresponding to the instruction, including:
• loading the token from the new shadow stack;
• performing one or more checks, including:
• checking that a portion of the token matches a portion of the memory address and that a least significant bit of the token has a value of one;
• causing a fault, if the check fails;
• and
• updating the SSP register with an SSP having a least significant bit replaced with a value of zero, if the check succeeds.

An apparatus comprising:

• a memory controller;
• and
• a processor coupled with the memory controller, the processor comprising:
• a shadow stack pointer (SSP) register to store a current SSP for a current shadow stack;
• a decode unit to decode an instruction to switch from the current shadow stack to a new shadow stack, the instruction having a memory operand to provide a memory address of a token stored on the new shadow stack;
• and
• an execution unit coupled with the decode unit, the execution unit to perform operations corresponding to the instruction, including to:
• load the token from the new shadow stack;
• check that a portion of the token matches a portion of the memory address and that a least significant bit of the token has a value of one;
• cause a fault, if the check fails;
• and
• update the SSP register with an SSP having a least significant bit replaced with a value of zero, if the check succeeds.

A system comprising:

• a system memory;
• and
• a processor coupled with the system memory, the processor comprising:
• a shadow stack pointer (SSP) register to store a current SSP for a current shadow stack;
• a decode unit to decode an instruction to switch from the current shadow stack to a new shadow stack, the instruction having a memory operand to provide a memory address of a token stored on the new shadow stack;
• and
• an execution unit coupled with the decode unit, the execution unit to perform operations corresponding to the instruction, including to:
• load the token from the new shadow stack;
• check that a portion of the token matches a portion of the memory address and that a least significant bit of the token has a value of one;
• cause a fault, if the check fails;
• and
• update the SSP register with an SSP having a least significant bit replaced with a value of zero, if the check succeeds.

A processor comprising:

• one or more caches;
• one or more control registers;
• a shadow stack pointer (SSP) register to store a first SSP for an active shadow stack;
• a decode unit to decode an instruction to switch from the active shadow stack to a new shadow stack, the instruction having a memory operand to provide a memory address of a token stored on the new shadow stack;
• and
• an execution unit coupled with the decode unit, the one or more caches, and the one or more control registers, the execution unit to execute the instruction to:
• load the token;
• perform a plurality of checks on the token, including to:
• determine whether an operating mode indicated by a bit value of a least significant bit of the token matches a current operating mode of the processor;
• and
• determine whether an SSP regenerated from the token matches the memory address;
• cause a fault if at least one of the checks fails;
• and
• update the SSP register with a value that matches the SSP regenerated from the token if the checks succeed.

A non-transitory machine-readable storage medium storing code that if executed causes a machine to perform operations, including to:

• store a current SSP for a current shadow stack in a shadow stack pointer (SSP) register;
• decode an instruction to switch from the current shadow stack to a new shadow stack, the instruction having a memory operand to provide a memory address of a token stored on the new shadow stack;
• and
• perform operations corresponding to the instruction, including to:
• load the token from the new shadow stack;
• check that a portion of the token matches a portion of the memory address and that a least significant bit of the token has a value of one;
• cause a fault, if the check fails;
• and
• update the SSP register with an SSP having a least significant bit replaced with a value of zero, if the check succeeds.