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AssigneeCornell University
InventorsJosé F. Martínez, Helena Caminal, Kailin Yang, Khalid Al-Hawaj, Christopher Batten
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A content-addressable processing engine, also referred to herein as CAPE, is provided. Processing-in-memory (PIM) architectures attempt to overcome the von Neumann bottleneck by combining computation and storage logic into a single component. CAPE provides a general-purpose PIM microarchitecture that provides acceleration of vector operations while being programmable with standard reduced instruction set computing (RISC) instructions, such as RISC-V instructions with standard vector extensions. CAPE can be implemented as a standalone core that specializes in associative computing, and that can be integrated in a tiled multicore chip alongside other types of compute engines. Certain embodiments of CAPE achieve average speedups of 14× (up to 254×) over an area-equivalent out-of-order processor core tile with three levels of caches across a diverse set of representative applications.
A content-addressable processing engine (CAPE) configured to execute a program having scalar operations and vector operations, the CAPE comprising:
An integrated circuit, comprising:
A method for executing a program using parallel processing in a content-addressable processing engine (CAPE), the method comprising:
Dependencies are inferred from the claim text.