Chip having updating bus and reading bus

A chip, comprising:

• a flash memory, recorded with first firmware, and content of the flash memory being configured to operate a function called by the chip to generate a function return value, wherein
• the chip is configured to
• generate a function address of a function call,
• map the function address to an operation address,
• cache the function return value generated in the flash memory into a cache memory according to the operation address,
• read the function return value from the cache memory via a first bus, and
• stop reading the function return value from the cache memory via the first bus upon the first firmware in the flash memory being updated via a second bus, different from the first bus, wherein
• upon receiving an update instruction, the chip is further configured to generate and reply a void return value conforming to a format of the function return value of the function to replace the function return value.

A chip, comprising:

• a flash memory, recorded with first firmware, and content of the flash memory being configured to operate a function called by the chip to generate a function return value, wherein
• the chip is configured to
• read the function return value via a first bus, or update the first firmware in the flash memory via a second bus, different from the first bus, and
• generate a void return value conforming to a format of the function return value of the function to replace the function return value upon the first firmware in the flash memory being updated via the second bus, wherein
• the first firmware in the flash memory is updated when the chip receives an update instruction from a mouse key or an external host.