Signal processing circuit, signal processing device, and signal processing method to suppress power consumption

A signal processing device, comprising:

• a plurality of multiply-accumulation operation circuits each configured to:
• subject each of a plurality of signals to a first multiply-accumulation operation to subject each of the plurality of signals to multiplication by a first-group coefficient and then accumulation to output each of a plurality of first signals;
• and
• subject each of the plurality of signals to a second multiply-accumulation operation to subject each of the plurality of signals to multiplication by a second-group coefficient and then accumulation to output each of a plurality of second signals;
• and
• a signal processing circuit having a plurality of first circuits and a second circuit, wherein
• the plurality of first circuits is electrically connected to the plurality of multiply-accumulation operation circuits, respectively,
• each of the plurality of first circuits includes:
• a first-time-length-signal output circuit configured to output a first time-length signal representing a time length between first timing at which a first signal of the plurality of first signals changes and second timing at which a second signal of the plurality of second signals changes;
• and
• a second-time-length-signal output circuit configured to output the first time-length signal as a second time-length signal at timing based on a control signal,
• the second circuit is configured to output the second time-length signal having the longest time length among a plurality of second time-length signals output from the plurality of first circuits, respectively.

A signal processing method, comprising:

• outputting, by a first time-length signal output circuit of a plurality of first circuits, a first time-length signal representing a time length between first timing at which a first input signal changes and second timing at which a second input signal changes;
• outputting, by a second time-length signal output circuit of the plurality of first circuits, the first time-length signal as a second time-length signal at timing based on a control signal;
• and
• outputting, by a second circuit, the second time-length signal having the longest time length among a plurality of second time-length signals output respectively from the plurality of first circuits.