US 12,001,773 B2Granted

Automated system and method for circuit design

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsShin-Chi Chen, King-Ho Tam, Yu-Ze Lin, Huang-Yu Chen

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Abstract

A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.

Claims20

Dependent claims

A method for optimizing a physical layout of an integrated circuit (IC) device, comprising:

(a) providing a plurality of values for an input variable parameter of the IC device;
(b) generating a plurality of layouts of the IC device corresponding to the respective values for the plurality of input variable parameter;
(c) computing a plurality of values for an output variable parameter corresponding to the plurality of input variable parameters based on the corresponding layout;
(d) determining a limiting condition on the value of the output variable parameter;
(e) determining at least one additional value for the input variable parameter based on the plurality of values for the input variable parameters, the values of the corresponding output variable parameter, and the limiting condition;
(f) repeating steps (b) through (e), with the additional value for the input variable parameter included in the plurality of input values, until a predetermined condition relating to the output variable parameter is met;
and
(g) generating, using at least one of the at least one value determined in step (e) for the input variable parameter, a layout of the IC device.

5 more elements

A system, comprising:

a processor;
and
computer readable media accessible by the processor and storing instructions that when executed by the processor implement a method that includes
(a) providing a plurality of values for an input variable parameter of the IC device;
(b) generating a plurality of layouts of the IC device corresponding to the respective values for the plurality of input variable parameter;
(c) computing a plurality of values for an output variable parameter corresponding to the plurality of input variable parameters based on the corresponding layout;
(d) determining a limiting condition on the value of the output variable parameter;
(e) determining at least one additional value for the input variable parameter based on the plurality of values for the input variable parameters, the values of the corresponding output variable parameter, and the limiting condition;
(f) repeating steps (b) through (e), with the additional value for the input variable parameter included in the plurality of input values until a predetermined condition relating to the output variable parameter is met;
and
(g) generating, using at least one of the at least one value determined in step (e) for the input variable parameter, a layout of the IC device.

8 more elements

A method, comprising:

computing, using a first EDA tool and from a post-route layout of an electronic circuit, a first set of values for a performance parameter for the electronic circuit;
and
computing a set of values for one or more electrical characteristics of the circuit by:
(a) providing a set of input values of the one or more electrical characteristics;
(b) computing, using a second EDA tool and the set of input values of the electrical characteristics, a second set of values of the performance parameter for the electronic circuit;
(c) determining a limiting condition on values of the performance parameter;
(d) comparing the second set of values of the performance parameter with the first set of values of the performance parameter, and modifying the set of input values of the electrical characteristics by a Bayesian optimization process, subject to the limiting condition;
(e) repeating steps (b) through (d) until the second set of values of the performance parameter bares a predetermined relationship with the first set of values of the performance parameter;
and
(f) generating, using the set of modified input values of the electrical characteristics, a modified layout of electronic circuit.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/295,085Filed 3 Apr 2023 · continuation
Priority: 27 May 2021
Published: US 2023/0237238 A127 Jul 2023
Granted: 4 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/31
Circuit design: design entry, e.g. editors specifically adapted for circuit design
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…

Family

Application17/331,825Parent of this continuation · filed 27 May 2021
US 2023/0237238 A1Pre-grant publication · published 27 Jul 2023
US 11,620,426 B2Parent of this continuation
US 2022/0382946 A1Published application
US 12,001,773 B2This patent

From the US filing history. Foreign family members aren’t listed.

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